1. Field of the Invention
The present invention relates to a semiconductor memory having an error correction function.
2. Description of the Related Art
A semiconductor memory having an error correction function has regular cell arrays storing externally supplied data and parity cell arrays storing parity data of data written to the regular cell arrays. The parity data are generated by a parity generation circuit according to the write data. Data read from the regular cell arrays are error-corrected by an error correction circuit according to the parity data. It is not generally easy to write desired data to the parity cell arrays, which makes a test of the parity cell arrays difficult.
As an art for easier testing of the parity cell arrays, for example, an art of forcibly inverting part of logical values of parity data to generate a pseudo error is disclosed (for example, Japanese Unexamined Patent Application Publication No. Hei 2001-351398 (Patent document 1)). Another art disclosed is an art in which a semiconductor memory is provided with an external parity data terminal for data read/write to/from a parity cell array in order to allow a desired pattern to be written to the parity cell array, and data are directly read/written from/to the parity cell array in a test mode (for example, Japanese Unexamined Patent Application Publication No. Hei 5-54697 (Patent document 2)).
The present invention was made to overcome the following problems. A semiconductor memory in Patent document 1 inverts part of bits of the parity data generated by a parity generation circuit. The parity data are generated as a result of logical operation on regular data written to regular cell arrays. Therefore, it is not possible to write desired data patterns to the parity cell arrays only by inverting part of the bits of the parity data.
In Patent document 2, it is possible to write desired patterns to the parity cell arrays. However, it is not possible to write desired patterns while a parity generation circuit and an error correction circuit are kept effective. In other words, it is not possible to write desired patterns to the parity cell arrays while the semiconductor memory is kept in an actual operation state. Moreover, forming the external parity data terminal (test pad) leads to an increase in chip size.
It is an object of the present invention to facilitate conducting a test of a semiconductor memory by writing desired data patterns to parity cell arrays. Another object is to write desired data patterns to the parity cell arrays while an error correction function is kept effective.